Gerry's Altera Hardware Projects - Currently Under Development
So before Going any further, I may have referred you to this page due to fact that you have had the idea to Reverse Engineering the Altera LP6 Logic Programming card or perhaps design a dedicated Programming Module devoted to ERASE/Resetting the JTAG Ports for various Altera MAX CPLD components.
Well the fact remains I started on both of these projects many years ago and they are still on my Agenda. Time in the Lab is hard to get these days with Work and Regular Life getting in the way.
You and countless others have contacted me several times with this Idea.
You all ask me to either Loan my LP6 card out to you... so you can reverse engineer it... or if I'm willing to sell it.
Clearly this is something many of us Tech's have desired to build for a long time. Seems we all think alike. :)
As for the LP6 Logic card Clone Project...
To this point I have removed the 3 CPLDs from the card, and I was able to successfully download the data to .pof image files, so their security bits were not set.
The rest is simply to reverse engineering the PCB schematic and other components used for the ISA card.
I am working on this (time permitting) and my plan from the beginning is to provide the plans and schematics open source on my website
as a DIY project for all of us to take a wack at building our own LP6 Clone. :)
As I have told every other person who has contacted me on this subject, due to the rarity of the LP6 card, I have no plans on lending it out or selling it.
Rest assured, I will provide the schematics open source on my Website once it is completed.
As for the "Altera MAX CPLD "ERASE" circuit Project"...for resetting Altera MAX 7000 series CPLD's
This is also an ongoing project of mine.
So for those of you that may not be aware, The Altera MAX 7000 series of chips have a particular programming Port on them
(5-Pins Shown Below highlighted in Yellow) called the JTAG interface port.
This port allows the chips to be Programmed/Read using a very cheap programmer called the Altera USB-Blaster.
This device costs about $10 on Ebay. (Shown Below)
Many people have had the problem of their Altera MAX7000 chips JTAG lines being locked. Sometimes these devoted pins are programmed to be used as Extra I/O pins. This is know as the "JTAG-LOCKOUT" state.
When used as I/O pins, the JTAG option is disabled. This means that once configured in this manner you can no longer use the USB-BLASTER and the
JTAG Programming Port to program the CPLD. In order to use it again, the Chips must be Erased to re-enable these JTAG pins.
Once the JTAG Port is enabled.... You are then able to use the cheap $10 JTAG programmer once again.
Problem is the ERASE function can only be performed by the Altera MPU or another Universal Programmer like the DATA I/O Unisite or Labsite.
So many people have wanted me to reverse engineer the Signals required that perform the ERASE function on the Chip and then send it to them so that
they can program a Micro-Controller to replicate the ERASE Signals. And of course they imagine a Fancy Enclosure with a Big Red Button on it that is labeled "ERASE".
They also talk about having a Devoted PLCC Socket underneath it for their Chip. Either that or they would have an I/O port for interfacing various CPLD's Sockets for connecting other Adapters.
Well, the fact again is that I had the same idea many years ago and it is also already an ongoing project of mine.
It's in the works.
It seems us technical minded always come up with the same ideas. :)
So again, I will release both of these Projects as a "DIY Project" on my Website once they are completed.
:) Cheers Folks!